1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (IC) and a method of designing the same, more particularly relates to a semiconductor IC and its design method capable of avoiding erroneous operation caused by clock skew by a simpler operation and less steps and decreasing the turnaround time (TAT) in the design of the layout.
2. Description of the Related Art
In semiconductor its, the signal propagation delay caused by interconnections is becoming greater in proportion to the overall signal propagation delay along with the increasing miniaturization in the fabrication process. Further, the signal propagation delay caused by the signal interconnections depends to a great extent on the results of the layout. As a result, the amount of the clock skew cannot be estimated precisely without knowing the result of the layout.
On the other hand, when clock skew occurred in a flip-flop of a semiconductor IC, erroneous operation caused by insufficient holding time sometimes occurs in a flip-flop supplied with the clock. For this reason, it is necessary to adjust for the clock skew by inserting delay elements into the logical net, that is, the path of the signal interconnections, for flip-flops with insufficient holding time based on the results of validation after the layout (simulation of logic taking into consideration timing information).
Below, an explanation will be made of an example of the erroneous operation caused by clock skew in a semiconductor IC. FIG. 1 is a circuit diagram of a shift register showing an example of cascade connected flip-flops controlled in timing by the same clock.
The shift register of the related art constitutes a first flip-flop F31 and a second flip-flop F32 of the same type. The first flip-flop F31 is controlled by a clock CK1, while the second flip-flop F32 is controlled synchronously by a clock CK2. Note that the clocks CK1 and CK2 are clocks of the same system (clocks in same clock tree in semiconductor IC). It is assumed that a signal propagation delay, that is, clock skew TSK, occurs between the clocks CK1 and CK2 due to the clock signal interconnections, clock buffers etc.
In the shift register of this related art, there is no combination logical gate circuit for delaying the signals on the signal line between the first flip-flop F31 and the second flip-flop F32, so this configuration is particularly susceptible to erroneous operation.
FIGS. 2A to 2D are waveform diagrams of signals in the flip-flops shown in FIG. 1. Input data changing from D1 to D2 to D3 etc. is supplied to the data input terminal D of the first flip-flop F31 from a data input terminal DT. The input data is set at the rising edge of the clock CK1. Accordingly, in the first flip-flop F31, the data D2 is held in the first cycle and the data D3 is held in the second cycle. As shown in FIG. 2B, the data held by the first flip-flop F31 is output from the data output terminal Q delayed from the rising edge of the clock CK1 by exactly a signal propagation delay TF31D of the first flip-flop F31.
The data output from the first flip-flop F31 is supplied as it is to a data input terminal D of the second flip-flop F32 and set at the rising edge of the clock CK2. From the viewpoint of the original function of a shift register, it is necessary that the second flip-flop F32 holds the data D1, held by the first flip-flop F31 in the previous cycle, in the first cycle and the data D2, held by the first flip-flop F31 in the first cycle, in the second cycle.
As shown in FIGS. 2A and 2C, however, a timing deviation occurs between the clocks CK1 and CK2 due to the clock skew TSK. Also, there is a signal propagation delay time TD12 caused by the signal interconnections from the data output terminal Q of the first flip-flop F31 to the data input terminal D of the second flip-flop F32. At the data input terminal D of the second flip-flop F32, a change of data, for example, a change from data D1 to D2 during the first cycle, becomes finalized after the elapse of the time of TF31D+TD12 from the rising edge of the clock CK1. Accordingly, at the rising edge of the clock CK2, the data at the data input terminal D of the second flip-flop F32 becomes the data held by the first flip-flop F31 during that cycle. This means that in the first cycle, the data D2 is held, while in the second cycle, the data D3 is held and that the first flip-flop F31 and the second flip-flop F32 hold the same data in the same cycle. The shift register is consequently unable to perform its original function and erroneous operation occurs.
Note that in this example of a shift register of the related art, erroneous operation may occur when the following condition is satisfied taking into account the setup time TF32S and the holding time TF32H of the second flip-flop: EQU TSK&gt;TF31D+TD12+TF32S-TF32H
Further, for reference, FIG. 3 is a circuit diagram of a logical cell of a flip-flop used when the shift register of this example of the related art is incorporated in a semiconductor IC. The first flip-flop F31 and the second flip-flop F32 are constituted as shown in FIG. 3 inside the semiconductor IC. In FIG. 3, the flip-flop is constituted by an inverter 308 receiving a clock CK and generating an internal clock CKN of negative logic, an inverter 309 receiving the internal clock CKN of negative logic and generating an internal clock CKP of positive logic, clocked inverters 301 and 304 controlled by the clock CKP of positive logic, clocked inverters 302 and 303 controlled by the clock CKN of negative logic, and inverters 305, 306, and 307.
As explained above, in designing a semiconductor IC, it is necessary to adjust for the clock skew according to the result of the validation after layout design by inserting delay elements into the logic net for the flip-flops with insufficient holding times. In the semiconductor IC and its design method of the related art, the area available in the layout has been decreasing along with the increase of the number of gates and interconnection layers in the semiconductor IC. This has made it extremely difficult to insert new delay elements. Furthermore, there was the disadvantage that the time for re-layout greatly increased and, as a result, the TAT of the layout design of a semiconductor IC has tremendously deteriorated.
Further, after re-layout, the insertion of delay elements or the change in disposition of the elements around the inserted delay elements sometimes caused a new possibility of erroneous operation such as holding time errors at other points. As a result, error sometimes could not be eliminated.